Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-02
2001-04-10
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S228000, C438S232000, C438S298000
Reexamination Certificate
active
06214674
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a high-voltage device that is suitable to apply in a low-voltage device, and more particularly to a method of fabricating a high-voltage device wherein a well formed by ion implantation is used as a drift region.
2. Description of the Related Art
As the size of the device is reduced, the reduced channel length shortens the desired time of the transistor during operation. The problem of short channel effect due to the reduced channel length gradually becomes more serious. According to the formula of electrical field=voltage/length, when the channel length of the transistor is reduced and the voltage is fixed, the energy of the electrons in the channel rises due to the enhancement of the electrical field. On the other hand, the electrical field is also enhanced, raising the energy of the electrons in the channel, when the voltage is increased and the channel length is fixed. Both of these situations may cause electrical breakdown.
For example, devices used for drivers of digital versatile disk (DVD) and liquid crystal display (LCD) need to endure a high voltage of about 12-30V. Generally, a high-voltage device uses an isolation region and a drift region under the isolation region to increase the distance between a source/drain region and a gate, so that the device can be operated normally under a high voltage.
FIGS. 1A-1D
are schematic, cross-sectional views of fabrication of a high-voltage device as known in the prior art. Referring to
FIG. 1A
, an N-type semiconductor substrate (not shown) is provided, and a well
10
having P-type impurity is formed in the semiconductor substrate. A pad oxide layer
20
is formed on the well
10
, and a silicon nitride layer
30
is then formed on the pad oxide layer
20
.
Referring to
FIG. 1B
, the silicon nitride layer
30
is patterned by a photoresist layer
40
. A portion of the silicon nitride layer
30
is then removed to form a silicon nitride layer
50
on the pad oxide layer
20
, and a portion of the well
10
is exposed. N-type ions are implanted into the exposed well
10
to form a drift region
60
having N-type ions.
Referring to
FIG. 1C
, the photoresist layer
40
is removed. Using the silicon nitride layer
50
as a mask, a field oxide layer
70
with a bird's beak of each side of the silicon nitride layer
50
is grown on the drift region
60
. The N-type ions in the drift region
60
are driven in the well
10
at a high temperature to broaden the drift region
60
.
Referring to
FIG. 1D
, the silicon nitride layer
50
and the pad oxide layer
20
are then removed. A thin oxide layer
80
is formed on the well
10
to serve as a gate oxide layer. A polysilicon layer
90
serving as a gate is formed on the well
10
by photolithography. Ion implantation with N-type ions of low dosage and high energy is performed on the well
10
, and a drift region
100
having N-type ions is then formed by driven-in thermally. N-type ions having high dosage and low energy are implanted into the well
10
beside the gate
90
to form a source region
110
and a drain region
120
.
As shown in
FIG. 1D
, in order to raise the breakdown voltage of the device, it is necessary to form multiple masks to fabricate the structure of the drift region. Fabrication of masks for the drift region consumes time and money, to the extent that throughput cannot be increased.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method of fabricating a high-voltage device that is compatible with the process of fabricating a low-voltage device. The fabrication of masks can be reduced in the high-voltage device process and the cycle time can also be decreased.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating a high-voltage device suitable for a low-voltage device. A substrate of a first type impurity is provided, and a first well of a second type impurity is formed within the substrate in a high-voltage device region. Second wells of the first type impurity are formed within the first well, and a third well of the first type impurity is formed within the substrate in a low-voltage device region wherein the second wells serve as a drift region of the high-voltage device region. A field implantation of the second type impurity is performed on the substrate and field oxide layers are formed on the substrate. A first gate is formed on the substrate between field oxide layers of the high-voltage device region, and a second gate is formed on the substrate of the low-voltage device region. A first source/drain region is formed within the second wells beside the field oxide layers of the first gate, and the second source/drain region is formed beside the second gate. A doped region of the first type impurity is formed within the second well in the low-voltage device region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 4818719 (1989-04-01), Yeh et al.
patent: 5545577 (1996-08-01), Tada
patent: 5550064 (1996-08-01), Yang
patent: 5622878 (1997-04-01), Beasom
patent: 5789788 (1998-08-01), Ema et al.
patent: 5965921 (1999-10-01), Kojima
patent: 5976922 (1999-11-01), Tung
Trinh Michael
United Microelectronics Corp.
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