Coating apparatus – Control means responsive to a randomly occurring sensed... – Temperature responsive
Reexamination Certificate
1999-05-27
2001-06-05
Mayes, Curtis (Department: 1734)
Coating apparatus
Control means responsive to a randomly occurring sensed...
Temperature responsive
C118S667000, C118S620000, C118S058000, C118S320000, C427S559000
Reexamination Certificate
active
06240874
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor processing apparatus and more particularly, it relates to a resist coating/developing processing method and apparatus for a wafer track system which integrates an edge exposure unit and a hot/cool plate unit so as to increase the throughput.
As is generally known in the art, a series of processes are required to be performed during the manufacturing of a semiconductor device. One such process is referred to as a “photolithographic or resist process” in which a resist coating is applied to a wafer, the wafer is then exposed, and thereafter the wafer is developed. There are several known types of systems which are commercially available for performing the resist coating/developing processing on a semiconductor wafer. For example, in industrial semiconductor fabrication facilities, there are used normally automated photoresist processing systems sometimes called “wafer track systems.” Such a prior art wafer track system is illustrated in FIG.
1
.
As can be seen, the wafer track system
10
includes a loader station
12
for loading and unloading cassettes containing wafers to be processed, a resist coating station
14
for applying a coat of positive tone resist, a heat treatment station
16
and a developing station
18
for developing the exposed wafer and rinsing the developed circuit pattern. The heat treatment station
16
includes a hot plate unit and/or a cool plate unit for controlling the wafer to be at a predetermined temperature. Further, a wafer edge exposure station
20
is positioned in a suitable arrangement with the loader station
12
, resist coating station
14
, heat treatment station
16
, and developing station
18
so as to perform the series of processes in an effective manner. The wafer edge expose station
20
is used to expose the resist coating at the peripheral edge portion of the wafer so as to make it base soluble for subsequent processes.
A photolithographic process flow diagram
200
for performing the resist coating/developing process steps as shown in
FIG. 2
, which is utilized in the wafer track system of
FIG. 1
, will now be described. Before the wafer is primed in step
202
of
FIG. 2
, it is generally known that a dehydration bake step (pre-treatment step) is required so as to remove fluids from the wafer before subsequent resist coating/developing processing steps can be carried out. In this pre-treatment step, the wafer stored in the cassette is moved to a hot plate or infrared lamp oven where baking off most of the absorbed water on the surface of the wafer occurs at approximately 150-200° C. in either a vacuum or a dry nitrogen atmosphere. After the dehydration baking step, the wafer is primed in the step
202
with hexamethyldisilazane (HMDS) which acts as an adhesion promoter. In other words, this priming will improve the adhesion of the photoresist to the wafer so as to reduce the amount of undercutting during the etching process.
After the wafer is primed in the step
202
, the wafer is moved to a cool plate as shown in step
204
in which the wafer is cooled down to a predetermined temperature. Next, the wafer is coated with a photoresist, such as a polyimide-based resist having a relatively high viscosity in step
206
. The most common method for applying the photoresist is referred to as “spin coating.” Initially, the wafer is mounted on a spin chuck, which is a flat, hollow metal disc connected to a vacuum line. The spin chuck has a number of small holes disposed on its surface. When the wafer is placed on the surface of the chuck, the vacuum holds the wafer in contact engagement with the chuck. Then, a predetermined amount of resist is disposed and spun onto the surface of the wafer. After the wafer is coated with resist, the wafer is transferred to a hot plate in step
208
for a “soft bake” operation. This baking operation is used to drive out most of the solvents in the photoresist and to establish the exposure characteristics.
Following the soft bake, the wafer is cooled on a cool plate to a desired temperature in step
210
and then is exposed so as to render the wafer edge water soluble in step
212
. Next, in step
214
a mask exposure is performed so as to apply a circuit pattern to the photoresist. After the step
214
, a post exposure bake or “hard bake” operation is performed in step
216
so as to make the photoresist that remains impervious to etchents. Then, the wafer is again cooled on a cool plate to a desired temperature in step
218
. Next, the wafer is developed in step
220
where a developing solution is applied to the upper surface of the wafer which has the resist coating already applied, followed by a rinse solution so as to wash away the developing solution. After the developing step
220
, the wafer is transferred to a hot plate in step
222
so as to perform a hard bake for hardening the resist against further energetic processes. Finally, the wafer is cooled down to a predetermined temperature in the cool plate as shown in step
224
.
In view of the number of various processing steps that the wafer is required to be passed through during fabrication as discussed above, it will be noted that the throughput for the wafer track system of
FIG. 1
is a function of the required number of overall processing steps (steps
202
-
224
) and the amount of time that is spent in each of the processing steps. One way of increasing the throughput of the track system is to provide multiple identical processing units for performing the same process so that the wafer can be processed in parallel. A second way of increasing the throughput is to reduce the amount of time that is being spent in each processing unit.
Each of these two ways has its own inherent disadvantages. The inventor of the present invention has thus developed a third way of increasing the throughput of the wafer track system by integrating or combining together two of the separate individual processing units into a new single integrated processing unit having the functionality of the two separate processing units.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a resist coating/developing processing method and apparatus for a wafer track system which has an increased throughput over the conventional track system.
It is an object of the present invention to provide a resist coating/developing processing method for a wafer track system which integrates together two separate individual processing units into a new single integrated processing unit having the functionality of the two separate processing units.
It is another object of the present invention to provide a resist coating/developing processing method and apparatus for a wafer track system which integrates a wafer edge exposure unit and a temperature control plate unit so as to increase its throughput.
It is still another object of the present invention to provide a resist coating/developing processing method and apparatus for a wafer track system which integrates a wafer edge exposure unit and another processing unit located between a resist coating unit and a resist development unit into a single integrated processing unit.
In a preferred embodiment of the present invention, there is provided an improved resist coating/developing processing method for use in a wafer track system so as to increase its throughput. A photoresist is applied in a resist coating processing unit to a wafer. An integrated heat treatment/wafer edge exposure processing unit is used to heat treat the wafer and expose the wafer edge after the photoresist has been applied. A developing solution is applied to the wafer in a resist development processing unit so as to remove the exposed resist after the wafer has been heat treated and exposed.
REFERENCES:
patent: 5639301 (1997-06-01), Sanada et al.
patent: 6089763 (2000-07-01), Choi et al.
Advanced Micro Devices , Inc.
Chin Davis
Lorengo J. A.
Mayes Curtis
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