Stacked mask integration technique for advanced CMOS transistor

Details Stacked mask integration technique for advanced CMOS transistor Stacked mask integration technique for advanced CMOS transistor

1997-12-09

1999-08-31

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438514, 438682, H01L 21336

Patent

active

059465794

ABSTRACT:
A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including a dielectric layer, a polysilicon layer and a masking layer. An opening is preferably formed in the masking layer, the opening defining the location of the gate conductor. The width of the opening may be narrowed by the use of spacers. A portion of the polysilicon layer defined by the opening is implanted with an n-type impurity. A silicide layer is formed upon the upper surface of the exposed polysilicon layer. An oxide layer is formed over the silicide layer. The polysilicon layer is etched such that a gate conductor is formed underneath the oxide layer. LDD areas and source/drain areas are subsequently formed adjacent to the gate conductor.

REFERENCES:
patent: 5576228 (1996-11-01), Chen et al.
patent: 5817560 (1998-10-01), Gardner et al.
patent: 5830801 (1998-11-01), Shiralagi et al.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, pp. 219-222, 441-443, Jan. 1986.

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