Semiconductor memory device and method of data transfer therefor

Details Semiconductor memory device and method of data transfer therefor Semiconductor memory device and method of data transfer therefor

1994-05-02

1996-01-02

Whitfield, Michael A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365222, 36523003, 36523005, 36523009, 365233, 365239, 365240, G11C 700, G11C 800

Patent

active

054814960

ABSTRACT:
Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.

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patent: 4825411 (1989-04-01), Hamano
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patent: 4855959 (1989-08-01), Kobayashi
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K. Pinknam, "A High Speed Dual Port Memory with Simultaneous Serial and Random Mode Access for Video Applictions" IEEE Journal of Solid-State Circuit, vol. SC-19, No. 6 (Dec. 1984) pp. 999-1007.
K. Mashiko et al. "A CMOS Dual Port Memory With Serial Read/Write Function for Graphic Systems" IEEE Transactions on Consumer Electronics, vol. CE-32, No. 3 (Aug. 1986) pp. 636-643.

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