Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1984-09-07
1987-01-13
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365204, 365210, G11C 700
Patent
active
046369856
ABSTRACT:
In a semiconductor memory in which a large number of memory cells are arrayed in the shape of a matrix, arrangements are provided for a high-sensitivity read-out. In one embodiment, a writing circuit, a voltage amplifier and a sense amplifier are successively connected to a data line that connects input and output ends of the memory cells in an identical row, with the voltage amplifier being formed as a CTD voltage amplifier that is composed of two charge transfer gates and a driving gate located between them. In accordance with another embodiment, a charge supplying circuit and a charge transfer circuit can be coupled between the memory cells and the sense amplifier to allow information transfer without any substantial loss.
REFERENCES:
patent: 4363111 (1982-12-01), Heightley et al.
Aoki Masakazu
Horiguchi Masahi
Ikenaga Shin'ichi
Nakagome Yoshinobu
Ozaki Toshifumi
Hitachi , Ltd.
Popek Joseph A.
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