Method of making a semiconductor device with a stacked cell stru

Details Method of making a semiconductor device with a stacked cell stru Method of making a semiconductor device with a stacked cell stru

1997-07-14

2000-04-18

Dutton, Brian

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, 438564, H01L 218234, H01L 2120, H01L 2122, H01L 2138

Patent

active

060514663

ABSTRACT:
The semiconductor memory device comprises a field shield element isolation structure for defining a plurality of element regions electrically isolated from one another; a plurality of memory cells disposed in a matrix of rows and columns, each including a transistor having two impurity diffusion layers, a gate electrode and a capacitor; a plurality of bit lines extending in a row direction; a plurality of word lines extending in a column direction; a plurality of memory cell pairs, each formed in one of the element regions and including adjacent two of the memory cells disposed in the row direction, wherein each of the transistors of the two memory cells in each memory cell pair has two impurity diffusion layers, one of which is common to both the transistors and connected to one of the bit lines extending in the row direction immediately thereabove through a first pad polycrystalline silicon film; a second pad polycrystalline silicon film formed on the other impurity diffusion layer of each transistor so as to extend over a portion of the element isolation structure defining the element region and adjacent thereto in the column direction; and a lower electrode of a capacitor of each memory cell in each memory cell pair formed on and insulated from the bit line connected to the common impurity diffusion layer of the respective transistors and connected to the other impurity diffusion layer of the transistor through one of the second pad polycrystalline films.

REFERENCES:
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patent: 5172202 (1992-12-01), Kazuo
patent: 5350705 (1994-09-01), Brassington et al.
patent: 5591998 (1997-01-01), Kimura et al.
M. Sakao et al., A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb Drams, IEDM, IEEE, 1990 pp. 655-658, 12/90.

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