Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-06-30
1999-07-13
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438286, 438289, 438305, H01L 21336
Patent
active
059239875
ABSTRACT:
Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.
REFERENCES:
patent: 4062699 (1977-12-01), Armstrong
patent: 4173818 (1979-11-01), Bassous et al.
patent: 4939571 (1990-07-01), Nishizawa et al.
patent: 4949140 (1990-08-01), Tam
patent: 5486480 (1996-01-01), Chen
patent: 5536959 (1996-07-01), Kellam
patent: 5650340 (1997-07-01), Burr et al.
Yoshimura et al., "New CMOS Shallow Junction Well FET Structure (CMOS-SJET) for Low Power-Supply Voltage", Semiconductor Device Enginnering Laboratory, Japan, Proceedings of IEDM, pp.909-912, 1992.
Burr et al., "Energy Considerations in Multichip-Module based Multiprocessors", IEEE International Conference on Computer Design, pp. 593-600, 1991.
Aoki et al., "0.1 um CMOS Devices Using Low-Impurity-Channel transistors (LICT)", IEDM, pp. 9.8.1-9.8.3, 1990.
Burr et al., "Ultra Low Power CMOS Technology", NASA VLSI Design Symposium, pp. 4.2.1-4.2.13, 1991.
Burr, "Stanford Ultra Low Power CMOS", Symposium Record, Hot Chips V, pp. 7.4.1-7.4.12, Apr. 1993.
Burr et al., "A 200 mV Self-Testing Encoder/Decoder using Stanford Ultra-Low-POwer CMOS", IEEE International Solid State Circuits Conf., pp. 84-86, 1994.
"A New Lease on Life for Old-Fashioned Chips", Business Week, Science & Technology, pp. 100-101, Dec. 1993.
Okumura et al., "Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Voltage Controllability", IEEE Transactions on Elec. Dev., vol. 39, No. 11, 2541-2552, Nov. 1992.
Hunter et al., "A New Edge-Defined Approach for Submicrometer MOSFET Fabrication", IEEE Electron Device Letters, vol.EDL-2, No. 1, Jan. 1991.
Huang et al., "TFSOI Complementary BiCMOS Technology for Low Power Applications", IEEE Transactions on Electron Devices, vol. 42, No. 3, pp. 506-512, Mar. 1995.
Takana et al., "A Sub-0.1 um Grooved Gate MOSFET with High Immunity to Short-Channel Effects", IEEE Transaction on Electronic Device, vol. 42, No. 3, pp. 537-540, Dec. 1993.
Yan et al., "High Performance 0.1 um Room Temperature Si MOSFETs", Symp. on VLSI Tech. Dig. of Technical papers, pp. 86-87, 1992.
Nguyen Tuan H.
Sun Microsystems Inc.
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