Pattern generator for a semiconductor integrated circuit tester

Details Pattern generator for a semiconductor integrated circuit tester Pattern generator for a semiconductor integrated circuit tester

1998-04-30

2000-12-12

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

061612065

ABSTRACT:
A test pattern generator for a semiconductor integrated circuit tester comprises a DRAM for receiving and storing test pattern data in blocks and a SRAM for storing checking data in units, wherein each unit of checking data stored in the SRAM bears a predetermined relationship to a corresponding block received by the DRAM. A DRAM sequencer addresses the DRAM for reading the blocks of test pattern data in a predetermined order and a SRAM sequencer addresses the SRAM for reading the units of checking data from the SRAM. A validating circuit receives a block of test pattern data read from the DRAM and the corresponding unit of checking data read from the SRAM and provides an output which indicates whether the unit of checking data is in the predetermined relationship with the block.

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