Circuit for generating a clock signal to separate bit lines in a

Details Circuit for generating a clock signal to separate bit lines in a Circuit for generating a clock signal to separate bit lines in a

1992-11-06

1995-03-28

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Complementing/balancing

365196, 365203, G11C 700

Patent

active

054023785

ABSTRACT:
A semiconductor memory device using a low level supply voltage has separation gates for isolating adjacent bit lines. The device may be constructed with a circuit for receiving a high voltage supplied by a high voltage generator resident upon the chip so as to provide the separation gates with a voltage increased at least by the amount of the threshold voltage of the separation gates over the supply voltage.

REFERENCES:
patent: 4608670 (1986-08-01), Duvvury et al.
patent: 4791616 (1988-12-01), Taguchi et al.
patent: 4951256 (1990-08-01), Tobita
patent: 5020031 (1991-05-01), Miyatake
patent: 5023841 (1991-06-01), Akrout et al.
patent: 5091885 (1992-02-01), Ohsawa
patent: 5177708 (1993-01-01), Furutani et al.
patent: 5189639 (1993-02-01), Miyatake
Mosaid Design, "An Analysis of the Hitachi HM511000 1Mx1 CMOS DRAMs", Mar. 1988, p. 58.

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