Method for fabricating double silicide gate electrode structures

Details Method for fabricating double silicide gate electrode structures Method for fabricating double silicide gate electrode structures

1996-05-28

1998-03-03

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257388, 257394, 257408, 257413, 257630, 438180, 438588, 438630, 438655, H01L 2976, H01L 2956

Patent

active

057238936

ABSTRACT:
A method is described for fabricating field effect transistors (FETs) having double silicide gate electrodes and interconnecting lines for CMOS circuits. The method reduces the IR voltage drops and RC time delay constants, and thereby improves circuit performance. The method consists of forming FETs having gate electrodes and interconnecting lines from a multilayer made up of a doped first polysilicon layer, a first silicide layer (WSi.sub.2), and a doped second polysilicon layer. After patterning the multilayer to form the gate electrodes, a titanium (Ti) metal is deposited and annealed to form a second silicide layer on the gate electrodes, and simultaneously forms self-aligned Ti silicide contacts on the source/drain areas. The latitude in overetching the contact openings in an insulating (PMD) layer to the gate electrodes extending over the field oxide area is increased, and the contact resistance (R.sub.c) is reduced because of the presence of the WSi.sub.2 below the contact openings, even if the Ti silicide is completely removed during the contact etching.

REFERENCES:
patent: 5130266 (1992-07-01), Huang et al.
patent: 5192992 (1993-03-01), Kim et al.
patent: 5203957 (1993-04-01), Yoo et al.

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