Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-03-25
1998-03-03
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438626, 438629, 438639, H01L 214763
Patent
active
057233802
ABSTRACT:
A method is described wherein topography of semiconductor wafer surfaces is improved. This is accomplished by introducing a specific planarization technique after the deposition of the first level of metal. It is shown further that the technique involves a combination of oxide and spin-on-glass layers. The resulting dielectric system is etched back in such a way that the resulting two-tiered metal-oxide structure and the surface thereover offers a uniformly flat depth-of-field which in turn makes possible the use of submicron optolithographic tools for the ultra high density integrated circuit chips. In an attempt to improve further the required flatness for submicron technologies, it is shown that silicon nitride may be introduced at a judiciously chosen process step so as to minimize the propagation of surface irregularities from one layer to another through minimizing the so-called microloading effect. It is found that the presence of silicon nitride for this purpose also serves the purposes of eliminating, what are called, the "exploding vias".
REFERENCES:
patent: 4839311 (1989-06-01), Riley et al.
patent: 5006485 (1991-04-01), Villalon
patent: 5068207 (1991-11-01), Manocha et al.
patent: 5077238 (1991-12-01), Fujii et al.
patent: 5336640 (1994-08-01), Sato
patent: 5366850 (1994-11-01), Chen et al.
patent: 5382545 (1995-01-01), Hong
patent: 5444019 (1995-08-01), Chen et al.
patent: 5482900 (1996-01-01), Yang
patent: 5496771 (1996-03-01), Cronin et al.
S. Wolf et al, "Silicon Processing for the VLSI Era--vol. 2", Lattice Press, Sunset Beach, CA, pp. 65, 236.
Liu Lu-Min
Wang Chin-Kun
Ackerman Stephen B.
Bowers Jr. Charles L.
Gurley Lynne A.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
LandOfFree
Method of approach to improve metal lithography and via-plug int does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of approach to improve metal lithography and via-plug int, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of approach to improve metal lithography and via-plug int will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2247139