Process for fabricating layered superlattice materials and makin

Details Process for fabricating layered superlattice materials and makin Process for fabricating layered superlattice materials and makin

1995-03-17

2000-06-06

Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

361320, 361321, 361322, 365117, 365145, H01L 2912

Patent

active

06072207&

ABSTRACT:
A liquid precursor containing a metal is applied to a substrate, RTP baked, and annealed to form a layered superlattice material. Special polyoxyalkylated precursor solutions are designed to optimize polarizability of the corresponding metal oxide materials by adding dopants including stoichiometric excess amounts of bismuth and tantalum. The RTP baking process is especially beneficial in optimizing the polarizability of the resultant metal oxide.

REFERENCES:
patent: 4133778 (1979-01-01), Gray
patent: 4485180 (1984-11-01), Konoike et al.
patent: 5241191 (1993-08-01), Agostinelli et al.
patent: 5426075 (1995-06-01), Perino et al.
patent: 5478610 (1995-12-01), Desu et al.
patent: 5519566 (1996-05-01), Perino et al.
Dohlev, "Solid-State Superlattices", Scientific American, Nov. 1983, pp. 144-151.

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