Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-11-26
2000-09-05
Bowers, Charles
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438303, 438305, H01L 21336
Patent
active
061142107
ABSTRACT:
A CMOS semiconductor device is formed having an N-channel transistor comprising a drain region with a graded N-LDD junction. The graded N-LDD junction is obtained by plural ion implantations at different implantation dosages, energies and angles. The graded N-LDD junction reduces the electric field around the drain, thereby increasing the HCI lifetime without adversely impacting the short channel effect.
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D. Nayak et al., in "A Comprehensive Study of Performance and Reliability of P, As, and Hybrid As/P N-LDD Junctions for Deep-Submicron CMOS Logic Technology," IEEE Electron Device Letters , vol. 18, No. 6, 1997, pp. 281-283.
Luning Scott
Wu David
Advanced Micro Devices , Inc.
Bowers Charles
Chen Jack
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