Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-06-01
2000-09-05
Chaudhuri, Olik
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438397, H01L 2120
Patent
active
061142018
ABSTRACT:
The present invention is a method of manufacturing a high density capacitors for use in semiconductor memories. High etching selectivity between BPSG (borophososilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a multiple fin-shape capacitor with a plurality of horizontal fins and vertical pillars. First, a contact hole formed on a semiconductor substrate using an etching process. A first polysilicon layer is then deposited in the contact hole to form a plug. A composition layer consists of BPSG and silicon oxide formed on the substrate. Then a opening is formed in the composition layer to serve as a storage node. A highly selective etching is then used to etch the BPSG sublayers of the composition layer. Next, a second polysilicon layer is formed along the surface of the composition layer, the substrate and the plug. Then a SOG layer is formed along the surface of the second polysilicon layer. A CMP process is used to polish a portion of the SOG layer and a portion of the second polysilicon layer on the top of the composition layer. The SOG layer and the composition layer are subsequently removed by BOE solution. A dielectric film is then formed on the second polysilicon layer and the substrate. Finally, a third polysilicon layer is formed along the surface of the dielectric layer. Thus, a capacitor with a plurality of horizontal fins and vertical pillars is formed.
REFERENCES:
patent: 5170233 (1992-12-01), Liu et al.
patent: 5532182 (1996-07-01), Woo
patent: 5650351 (1997-07-01), Wu
patent: 5656536 (1997-08-01), Wu
patent: 5677222 (1997-10-01), Tseng
patent: 5770499 (1998-06-01), Kwok et al.
patent: 5789267 (1998-08-01), Hsia et al.
patent: 5817553 (1998-10-01), Stengl et al.
patent: 5834357 (1998-11-01), Kang
patent: 5843822 (1998-12-01), Hsia et al.
patent: 5851876 (1998-12-01), Jeng
patent: 5879987 (1999-03-01), Wang
patent: 5891772 (1999-04-01), Hsu
patent: 5907782 (1999-05-01), Wu
patent: 5909621 (1999-06-01), Hsia et al.
patent: 5998260 (1999-12-01), Lin
Wolf, Silicon Processing for the VLSI Era, Lattice Press, vol. 2, p. 223, 1990.
H. Watanabe et al., A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs 1992 IEEE, pp. 259-262.
Chaudhuri Olik
Duy Mai Anh
Texas Instruments--Acer Incorporated
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