Method for forming a semiconductor memory device with a capacito

Details Method for forming a semiconductor memory device with a capacito Method for forming a semiconductor memory device with a capacito

1997-01-16

1998-06-09

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438396, 438397, 148DIG14, H01L 218242

Patent

active

057633053

ABSTRACT:
A method of fabricating a semiconductor memory device having a capacitor. First, a first insulating layer is formed on a substrate to cover the transistor. Next, a second insulating layer and a first conductive layer are formed in order. The first conductive layer only covers a portion of the second insulating layer to form a branch-like conductive layer. Then, a third insulating layer is formed. An opening is next formed. A second conductive layer is filled into the opening and therefore electrically connected to the source/drain region of the transistor to form a trunk-like conductive layer. Next, the second and the third insulating layers are removed. After a dielectric film is formed on the exposed surfaces of the first and second conductive layers, a third conductive layer is formed on the dielectric film to form an opposed electrode.

REFERENCES:
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5077688 (1991-12-01), Kumanoya et al.
patent: 5089869 (1992-02-01), Matsuo et al.
patent: 5102820 (1992-04-01), Chiba
patent: 5126810 (1992-06-01), Gotou
patent: 5142639 (1992-08-01), Kohyama et al.
patent: 5155657 (1992-10-01), Oehrlein et al.
patent: 5158905 (1992-10-01), Ahn
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5172201 (1992-12-01), Suizu
patent: 5196365 (1993-03-01), Gotou
patent: 5206787 (1993-04-01), Fujioka
patent: 5266512 (1993-11-01), Kirsch
patent: 5274258 (1993-12-01), Ahn
patent: 5338955 (1994-08-01), Tamura et al.
patent: 5354704 (1994-10-01), Yang et al.
patent: 5371701 (1994-12-01), Lee et al.
patent: 5389568 (1995-02-01), Yun
patent: 5399518 (1995-03-01), Sim et al.
patent: 5438011 (1995-08-01), Blalock et al.
patent: 5443993 (1995-08-01), Park et al.
patent: 5453633 (1995-09-01), Yun
patent: 5460996 (1995-10-01), Ryou
patent: 5478768 (1995-12-01), Iwasa
patent: 5478770 (1995-12-01), Kim
patent: 5482886 (1996-01-01), Park et al.
patent: 5508222 (1996-04-01), Sakao
patent: 5521419 (1996-05-01), Wakamiya et al.
patent: 5523542 (1996-06-01), Chen et al.
patent: 5543346 (1996-08-01), Keum et al.
patent: 5550080 (1996-08-01), Kim
patent: 5561309 (1996-10-01), Cho et al.
patent: 5561310 (1996-10-01), Woo et al.
patent: 5572053 (1996-11-01), Ema
patent: 5595931 (1997-01-01), Kim
Ema et al., "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS", International Electron Devices Meeting, pp. 592-595, Dec. 1988.
Wakamiya et al., "Novel Stacked Capacitor Cell for 64-Mb DRAM", 1989 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70.
"Mini-Trenches in Polysilicon For Dram Storage Capacitance Enhancement", IBM Technical Disclosure Bulletin, vol. 33, No. 9, Feb. 1991.

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