Method of producing a MOS transistor

Details Method of producing a MOS transistor Method of producing a MOS transistor

1999-06-04

2000-12-12

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438306, 438307, 438230, H01L 21336

Patent

active

061598151

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates generally to a method for producing a MOS transistor having an HDD profile and a LDD profile.
2. Description of the Related Art
In order to avoid short-channel effects, MOS transistors with short channel lengths are usually produced in such a way that the source/drain regions have an LDD (lightly doped drain) profile and an HDD (heavily doped drain) profile. The LDD profile has a lower dopant concentration and a smaller depth than the HDD profile. However, the LDD profile reaches closer to the gate electrode and dictates the channel length of the MOS transistor. By contrast, the HDD profile has a lower connection resistance.
In order to produce a MOS transistor with LDD and HDD profile, a gate dielectric and a gate electrode are firstly structured on the surface of a substrate. Using the gate stack, and optionally thin spacers (for example 20 nm) as a mask, the LDD profile is produced by implantation. Next, thick spacers are formed on the sides of the gate stack. Using the gate stack with the thick spacers as a mask, the HDD profile is then produced by implantation (for example T. Ohguro et al., VLSI Techn. Dig. (1996), page 132 or Y. Nakahara et al., VLSI Techn. Dig. (1996) page 174).
The minimum depths which can be achieved for the dopant profiles are limited by the heat treatment steps, which are needed for annealing and activating the implanted dopant.


SUMMARY OF THE INVENTION

An object of the invention is to provide a method for the production of a MOS transistor, with which small depths can be achieved for the dopant profiles close to the channel area.
This object and other objects are achieved according to the invention by a method for the production of a MOS transistor, in which a gate dielectric and a gate electrode are formed on the main face of a substrate, which comprises silicon at least at the main face, a first auxiliary layer is deposited with essentially conformal edge coverage, a second auxiliary layer, which can be etched selectively with respect to the first auxiliary layer, is deposited with essentially conformal edge coverage, spacers are formed at the sides of the gate electrode by anisotropically etching back the second auxiliary layer, implantation is carried out to form first subregions for source/drain regions, the spacers are removed selectively with respect to the first auxiliary layer, the surface of the substrate is etched in the areas where the two subregions for the source/drain regions are subsequently formed, and second subregions for the source/drain regions are formed by in situ doped selective epitaxy, the second subregions having a lower dopant concentration and a smaller depth than the first subregions. Further refinements of the invention are provided by the first auxiliary layer being formed from SiO2 and/or Si3N4, and the second auxiliary layer being formed from polysilicon. Preferably, at least one n-channel transistor and one p-channel transistor are formed, the first subregions for the n-channel transistor are firstly formed by implantation and subsequent heat treatment, the area for the p-channel transistor being covered with a first mask, the first subregions for the p-channel transistor are formed, the area for the n-channel transistor being covered with a second mask, the second mask and the spacers are removed, the second subregions for the n-channel transistor are formed by implantation and subsequent heat treatment, the area for the p-channel transistor being covered with a third mask, a fourth mask, which covers the area for the n-channel transistor, is formed after the third mask has been removed, the surface of the substrate is exposed and subsequently etched in the area of the second subregions of the p-channel transistor, and the second subregions for the p-channel transistor are formed by in situ doped selective epitaxy.
In the method according to the invention, the source/drain regions of the MOS transistor each comprise a first subregion and a second subregion

REFERENCES:
patent: 4838993 (1989-06-01), Aoki et al.
patent: 5491099 (1996-02-01), Hsu
patent: 5599725 (1997-02-01), Dorleans et al.
patent: 5663083 (1997-09-01), O et al.
Questel Plus--Epoque 8912.
Parrillo et al., "Disposable Polysilicon LDD Spacer Technology", IEEE Transactions on Electron Devices, vol. 38, No. 1, Jan. 1991, pp. 39-46.
Borland, "Selective Silicon Deposition for the Megabit Age", Solid State Technology, Jan. 1990, pp. 73-78.
Nakahara et al., "Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS", Symposium of VLSI Technology Digest of Technical Papers, pp. 174-175.
Ohguro et al., "0.2 .mu.m analog CMOS with very low noise figure at 2 Ghz operation", Symposium on VLSI Technology Digest of Technical Papers, pp. 132-133.

Affiliated with

Also associated with

Rating

Method of producing a MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of producing a MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of producing a MOS transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-216250