Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-10-07
1999-11-02
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
059789476
ABSTRACT:
This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC.sub.-- RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC.sub.-- RSs corresponding to one or more RSB elements into a matrix such that each SBRIC.sub.-- RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC.sub.-- RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC.sub.-- RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.
REFERENCES:
patent: 5381419 (1995-01-01), Zorian
patent: 5570374 (1996-10-01), Yau et al.
patent: 5602878 (1997-02-01), Cross
Pest & CKT: CAD Tools for Implementing BIST, ATE and Instrumentation Conference (1990) by Meera M. Pradham and Paul R. Rutkowski.
"Simple And Efficient Algorithms For Functional RAM Testing" by Marian Marinescu, Computer Architecture Group, Paper 10.2, pp. 236-239.
Yervant Zorian, An Effective BIST Scheme for ROM's, IEEE Transactions on Computers, vol. 41, No. 5, May 1992.
Kim Ilyoung
Rutkowski Paul William
Zorian Yervant
Cady Albert De
Greene Jason
Lucent Technologies - Inc.
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