Tie-up and tie-down circuits with a primary input for testabilit

Details Tie-up and tie-down circuits with a primary input for testabilit Tie-up and tie-down circuits with a primary input for testabilit

1994-02-14

1995-08-22

Westin, Edward P.

Electronic digital logic circuitry

With test facilitating feature

326 38, 371 225, G06F 738, H03K 19173

Patent

active

054443911

ABSTRACT:
A semiconductor product logic chip (20) including a logic network (27-1) to be fed by a tie-up/tie down circuit (21-1). A tie-up/tie-down circuit is comprised of a non-inverting buffer book (22-1) whose input terminal (23-1) is controlled from the outside by a connection (25) to a primary input terminal (24) of the said chip. Its output terminal (26-1) is connected to said logic network. The primary input terminal is connected to a voltage supply means (29) capable of supplying a constant supply voltage VDD/GND in the SYSTEM mode and a supply voltage varying between VDD and GND, during the TEST mode. When the chip operates in the SYSTEM mode, the supply voltage means is the VDD/GND power supply, so that the primary input terminal is directly tied to the VDD/GND power supply. As a result, the tie-up/tie-down circuit generates a steady logic level "1"/"0" on its output terminal. Unlike, in the TEST mode, the voltage supply means consists of the tester generator so that the tie-up/tie-down circuit follows the tester stimuli sequence. As a result, the output terminal of the tie-up/tie-down circuit switches between the "1" and "0" logic levels depending on the tester stimuli. This allows the tester to detect all the stuck-at faults in the logic network. In this mode, the tie-up/tie-down function is not realized, since its output terminal is set to either the "0" and "1" logic levels.

REFERENCES:
patent: 4758746 (1988-07-01), Birkner
patent: 4780628 (1988-10-01), Illman
patent: 4812678 (1989-03-01), Abe
patent: 5023485 (1991-06-01), Sweeney
patent: 5250854 (1993-10-01), Lien
A. Motohara, et al., "Design for Testability for Complete Test Coverage" 8219 IEEE Design & Test of Computers, pp. 25-32, Nov. 1984.
Dick L. Liu, et al., "A CMOS PLA Design for Built-In Self-Test" vol. 3 1977 IEEE Inter. Symp. on Circuits & Systems, pp. 859-862, May 1987.
Anonymous, "Off Chip Receiver for Multi-Chip Module Testing" Research Disclosure Bulletin, vol. 285, #50, p. 41, Jan. 1988.

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