Method of making a self-aligned disposable gate electrode for ad

Details Method of making a self-aligned disposable gate electrode for ad Method of making a self-aligned disposable gate electrode for ad

1997-12-30

1999-11-02

Fahmy, Wael M.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438438, 257369, H01L 2131

Patent

active

059769246

ABSTRACT:
A method of fabricating an integrated circuit transistor in a substrate is provided wherein a self-aligned gate electrode is formed after the high temperature steps associated with sidewall spacer formation and source/drain anneal. A first dielectric layer is formed on a substrate. First and second source/drain regions are formed in the substrate and spaced laterally to define a channel region underlying the first dielectric layer. A second dielectric layer is formed on the substrate except where the first dielectric layer is positioned. The first dielectric layer is removed and a third dielectric layer is formed that overlies the channel region. A gate electrode is formed on the third dielectric layer. The first dielectric layer functions as a disposable gate electrode to facilitate self-aligned source/drain implant and sidewall spacer formation.

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Stanley Wolf and Richard N. Tauber, Silicon Processing for the VLSI Era, vol. 2--Processing Integration, pp. 144-152, 182-188, 318, 332-333, 419-439, Dec. 1990, Publication U.S.
Stanley Wolf and Richard N. Tauber, Silicon Processing for the VLSI Era, vol. 3--The Submicron MOSFET, pp. 367-407, Dec. 1995, Publicaton U.S.

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