Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-04-21
1999-03-23
Brown, Peter Toby
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438275, 438276, 438519, H01L 218236
Patent
active
058858741
ABSTRACT:
A method of making enhancement-mode and depletion-mode IGFETs is disclosed. The method includes providing a semiconductor substrate with first and second device regions, forming a gate material over the first and second device regions, implanting a dopant into the gate material such that a peak concentration of the dopant has a first depth in the gate material over the first device region and a second depth in the gate material over the second device region, and the first depth is substantially greater than the second depth, etching the gate material to form a first gate over the first device region and a second gate over the second device region after implanting the dopant into the gate material, forming sources and drains in the first and second device regions, and transferring the dopant into a first channel region in the first device region without transferring essentially any of the dopant into a second channel region in the second device region, thereby providing depletion-mode doping in the first channel region while retaining enhancement-mode doping in the second channel region. The dopant can be simultaneously implanted into the gate material over the first and second device regions using a displacement material over the gate material over the second device region. Alternatively, the dopant can be sequentially implanted into the gate material over the first device region with a first implant energy and into the gate material over the second device region with a second implant energy. Preferably, the dopant is transferred from the first gate into the first channel region by diffusion.
REFERENCES:
patent: 4085498 (1978-04-01), Rideout
patent: 4329186 (1982-05-01), Kotecha et al.
patent: 4725871 (1988-02-01), Yamazaki
patent: 5021356 (1991-06-01), Henderson et al.
patent: 5300443 (1994-04-01), Shimabukuro et al.
patent: 5512506 (1996-04-01), Chang et al.
patent: 5688722 (1997-11-01), Harrington, III
Silicon Processing for the VLSI Era--vol. 3: The Submicron MOSFET, by S. Wolf, published by Lattice Press, Sunset Beach. CA, 1995, pp. 554-555.
Advanced Micro Devices , Inc.
Brown Peter Toby
Guerrero Maria
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