Method for making openings in a passivation layer over polycide

Details Method for making openings in a passivation layer over polycide Method for making openings in a passivation layer over polycide

1999-05-26

2000-09-26

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438132, H01L 218242

Patent

active

061241652

ABSTRACT:
A method for making improved fuse elements by deleting redundant circuit elements on DRAM circuits is achieved. The method involves forming fuses from a second polycide layer having a Si.sub.3 N.sub.4 cap layer and sidewalls. Bit lines are also formed from the second polycide layer. After forming the node capacitors and the first metal (M1) interconnections, via holes are etched to M1 and concurrent fuse window openings are partially etched over the fuses. A tungsten metal plug in the via hole and a patterned second metal (M2) for interconnections are used to protect the via hole from overetching when the fuse window opening is completed. Next, a Si.sub.3 N.sub.4 layer and a polyimide layer are deposited to complete the passivation on the DRAM. The fuse window openings and openings to the bonding pads are etched using the polyimide layer as a single photoresist mask. This method reduces the number of masking steps, and the method also avoids metal residue that could cause shorts in the fuse area, while the Si.sub.3 N.sub.4 cap prevents moisture damage to the fuse. The HDP USG layer prevents moisture from entering neighboring circuits, and this enhances reliability of the chip.

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