Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-02-07
1999-10-19
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438233, 148DIG123, H01L 218238
Patent
active
059703350
ABSTRACT:
A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate includes, a) providing a semiconductor substrate; b) masking a desired first conductivity type region of the substrate while conducting second conductivity type doping into a desired second conductivity type active region of the substrate; c) providing an insulating layer over the substrate over the desired first conductivity type region and the second conductivity type doped region; d) patterning the insulating layer to provide a void therethrough to the desired first conductivity type region; e) filling the void with a first conductivity type doped polysilicon plug, the plug having a first conductivity type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.3, the desired first conductivity type region having a first conductivity type dopant concentration prior to the filling step which is in the range of from 0 ions/cm.sup.3 to 1.times.10.sup.19 ions/cm.sup.3 ; and f) annealing the substrate for a period of time effective to out-diffuse first conductivity type dopant impurity from the first conductivity type doped polysilicon plug into the substrate to form the desired first conductivity type active region having a first conductivity type dopant impurity concentration of at least 1.times.10.sup.20 ions/cm.sup.3 in the substrate. Methods of forming CMOS FET transistors, and SRAM and DRAM CMOS circuitry are also disclosed.
REFERENCES:
patent: 4707457 (1987-11-01), Erb
patent: 5145799 (1992-09-01), Rodder
patent: 5179033 (1993-01-01), Adan
patent: 5204279 (1993-04-01), Chan et al.
patent: 5422289 (1995-06-01), Pierce
patent: 5571733 (1996-11-01), Wu et al.
Dennison Charles
Helm Mark
Micro)n Technology, Inc.
Murphy John
Niebling John F.
LandOfFree
Semiconductor processing method of forming complementary n-type does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor processing method of forming complementary n-type , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor processing method of forming complementary n-type will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2068333