Method of forming an ultrathin gate dielectric

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438300, 438305, H01L 21336

Patent

active

060749199

ABSTRACT:
A method is provided for fabricating a transistor, the method including forming a semiconducting layer above a substrate layer, forming a first dielectric layer above the semiconducting layer and forming a sacrificial layer above the first dielectric layer. The method also includes forming an opening in the sacrificial layer, the first dielectric layer and the semiconducting layer to expose a channel region in the substrate layer. The method further includes forming a gate dielectric above the channel region in the substrate layer within the opening and forming a gate conductor above the gate dielectric within the opening. Moreover, the method includes removing the sacrificial layer to expose sides of the gate conductor and introducing a dopant into the semiconducting layer to form doped source/drain regions. In addition, the method includes forming dielectric spacers adjacent the gate conductor.

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patent: 5120668 (1992-06-01), Hsu et al.
patent: 5194926 (1993-03-01), Hayden
patent: 5597752 (1997-01-01), Niwa

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