Static information storage and retrieval – Read/write circuit – Differential sensing
Patent
1996-10-31
1998-04-21
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Differential sensing
365205, 365208, 327 57, G11C 700
Patent
active
057425523
ABSTRACT:
A semiconductor memory is disclosed having a primary memory array (12) and a dummy column (14) associated therewith that is comprised of a plurality of dummy memory cells (70). The dummy memory cells have a predetermined value stored therein and are sensed with a dummy sense amplifier (18). The dummy sense amplifier (18) has a predetermined offset disposed therein, such that it is in a predetermined state prior to the bit lines separating a sufficient amount to detect the logic state in the dummy memory cell, with an offset disposed therein. This offset prevents the state of the dummy sense amp from being changed until the bit lines are separated by a predetermined value. The primary sense amplifiers associated with the primary memory array (12) are not enabled until the dummy sense amplifier has detected the dummy bit lines as being separating by the predetermined amount. Once this bit line separation has been detected, the primary sense amplifiers are enabled, and the data stored in the accessed memory of the primary memory array (12) latched into the primary sense amplifiers.
REFERENCES:
patent: 4421996 (1983-12-01), Chuang et al.
patent: 4816706 (1989-03-01), Dhong et al.
Brady III Wade James
Donaldson Richard L.
Holland Robby T.
Popek Joseph A.
Texas Instruments Incorporated
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