Method for manufacturing a multi-layer wiring structure of a sem

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

438632, 438643, 438646, 438661, 438680, 438688, H01L 2128

Patent

active

058519173

ABSTRACT:
A wiring structure of semiconductor device and a method for manufacturing the same which fills up a contact hole of below one half micron. An insulating layer is formed on a semiconductor substrate, and a contact hole or a via hole is formed in the insulating layer. On the insulating layer, a first metal is deposited via a CVD method to form a CVD metal layer or a CVD metal plug filling up the contact hole. Then, the thus-obtained CVD metal layer or the CVD metal plug is heat-treated in a vacuum at a high temperature below the melting point of the first metal, thereby planarizing the surface thereof the CVD metal layer. A second metal is deposited via a sputtering method on the CVD metal layer or on the CVD metal plug to thereby form a sputtered metal layer. The contact hole is filled up with the first metal by the CVD method and then a reliable sputtered metal layer is deposited via a sputtering method. The wiring layer can be used for the semiconductor device of the next generation.

REFERENCES:
patent: 4673623 (1987-06-01), Gardner et al.
patent: 4784973 (1988-11-01), Stevens et al.
patent: 4803181 (1989-02-01), Buchmann et al.
patent: 4826754 (1989-05-01), Bobbio
patent: 4837183 (1989-06-01), Polito et al.
patent: 4924295 (1990-05-01), Kuecher
patent: 4970176 (1990-11-01), Tracy et al.
patent: 4976839 (1990-12-01), Inoue
patent: 5124780 (1992-06-01), Sandhu et al.
patent: 5169803 (1992-12-01), Miyakawa
patent: 5180687 (1993-01-01), Mikoshiba et al.
patent: 5233224 (1993-08-01), Ikeda et al.
patent: 5242860 (1993-09-01), Nulman et al.
patent: 5378660 (1995-01-01), Ngan et al.
Ono et al., Development of a Planarized Al-Si Contact Filling Technology, 1990 VMIC Conference (Jun. 12, 1990) pp. 76-82.
Pramanik et al., Effect of Underlayer on Sputtered Aluminum Grain Structure and Its Correlation With Step Coverage in Submicron VIAS, VMIC (Jun. 12-13, 1990) pp. 332-334.
Park et al., Al-Plaph (Aluminum-Planarization by Post-Heating) Process for Planarzied Double Metal CMOS Applications, 1991 VMIC Conference (Jun. 11-12, 1991) pp. 326-328.
Wolf, S., Silicon Processing for the VLSI Era--vol. II, Lattice Press, 1990, pp. 254-255.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for manufacturing a multi-layer wiring structure of a sem does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing a multi-layer wiring structure of a sem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing a multi-layer wiring structure of a sem will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2047158

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.