Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-07-18
1998-12-22
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438910, H01L 21336
Patent
active
058518932
ABSTRACT:
A transistor fabrication process is provided which derives a benefit from having barrier atoms incorporated in a lateral area under a gate oxide of the transistor in close proximity to the drain. To form the transistor, a gate oxide layer is first grown across a silicon-based substrate. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are removed to form a gate conductor and gate oxide, thereby exposing source-side and drain-side junctions within the substrate. An LDD implant is performed to lightly dope the source-side and drain-side junctions. An etch stop material may be formed upon opposed sidewall surfaces of the gate conductor, the upper surface of the gate conductor, and the source-side and drain-side junctions. Spacers may then be formed laterally adjacent the etch stop material located upon sidewall surfaces of the gate conductor. The unmasked portions of the source-side and drain-side junctions are heavily doped, resulting in source and drain regions that are aligned to the exposed lateral edges of the spacers. The drain-side spacer is removed and barrier atoms are forwarded through the exposed etch stop material and into a substrate/gate oxide interface region near the drain junction. The barrier atoms help reduce hot electron effects by blocking diffusion avenues of carriers (holes or electrons) from the drain-side junction into the gate oxide.
REFERENCES:
patent: 5464792 (1995-11-01), Tseng et al.
patent: 5552332 (1996-09-01), Tseng et al.
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5744371 (1998-04-01), Kadosh et al.
Fulford Jr. H. Jim
Gardner Mark I.
Advanced Micro Devices , Inc.
Chaudhari Chandra
Daffer Kevin L.
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