Method for fabricating compact contactless trenched flash memory

Details Method for fabricating compact contactless trenched flash memory Method for fabricating compact contactless trenched flash memory

1997-01-22

1998-12-22

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438264, H01L 21336

Patent

active

058518797

ABSTRACT:
A method for fabricating compact contactless trenched flash memory array for semiconductor EEPROM devices is disclosed. The flash memory array comprises a number of memory cell units. Each of the cell units comprises a body line, source and drain regions and a stacked gate constructed over a silicon wafer substrate. The source and drain regions are buried regions and the body line is isolated by the surrounding buried source/drain regions and trenches formed to cut deep down to the substrate of the wafer. The stacked gate includes a first polysilicon layer, an oxide-nitride-oxide configuration, a second polysilicon layer, a pad oxide layer and a nitride layer. The source and drain buried regions sandwiches the body line, and the stacked gate substantially sits directly atop the body line. The flash memory array is free from the serious problem of short channel effect.

REFERENCES:
patent: 5472893 (1995-12-01), Iida
patent: 5622881 (1997-04-01), Acocella
patent: 5631179 (1997-05-01), Sung
patent: 5679591 (1997-10-01), Lin et al.
"A Novel memory Cell Using Flash Array Contactless EPROM (FACE) Technology," 1990, IEDM, pp., 90-94.
"A NAND Structured Cell With A New Programming Technology For Highly Reliable 5-V Only Flash EEPROM," 1990, Symposium on VLSI Technology, pp., 129-130.

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