Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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36518901, 36523003, G11C 700

Patent

active

055196608

ABSTRACT:
There is disclosed a semiconductor memory device which can decrease precharge current and stably read out data, e.g., EEPROM, etc., having column line potential setting transistors connected between precharging transistors and their corresponding column lines. The column line potential setting transistor maintains precharging potential of the column line to a low value for suppressing instantaneous current by precharging to a low value and in a read cycle after precharge it further lowers the gate potential applied to the gate of the column line potential setting transistors to a value lower than a potential of the gate for the precharge period thereby prevent an erroneous operation by the capacitive coupling between column lines.

REFERENCES:
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patent: 4954987 (1990-09-01), Auvinen et al.
patent: 5228003 (1993-07-01), Tokuda
patent: 5309401 (1994-05-01), Suzuki et al.
patent: 5313434 (1994-05-01), Abe
Cuppens, Roger, et al., "A 256 kbit ROM With Serial ROM Cell Structure", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 3, Jun. 1983, pp. 340-344.

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