Method of manufacturing CMOS transistors

Details Method of manufacturing CMOS transistors Method of manufacturing CMOS transistors

1999-02-03

2000-07-18

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438227, 438232, 438683, 438685, H01L 218238

Patent

active

060906537

ABSTRACT:
The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a tilted angle relative to the normal line of the substrate is used. The tilted angle is about 30 to 90 degrees respect to the substrate. The ions pass through the spacers, gate oxide and into the substrate under a portion of the gate by controlling the energy of the ion implantation. The spacers also doped with ions during the implantation. The energy of the ion implantation is about 5 to 150 KeV, and the dosage of the ion implantation is about 5E12 to 2E15 atoms/cm.sup.2. The cap silicon nitride layer is then removed. Then, a refractory or noble metal layer is sputtered on the substrate, nitrogen doped oxide spacers and the gates. A first step thermal process is performed to form SALICIDE and polycide. Next, an ion implantation is utilized to dope ions into the SALICIDE and polycide films. A second step thermal process is employed to form a shallow source and drain junction.

REFERENCES:
patent: 5656519 (1997-08-01), Mogami
patent: 5759885 (1998-06-01), Son

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