Method to reduce timing skews in I/O circuits and clock drivers

Details Method to reduce timing skews in I/O circuits and clock drivers Method to reduce timing skews in I/O circuits and clock drivers

1997-09-30

2000-07-18

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

438283, 438279, 438585, H01L 21337

Patent

active

060906502

ABSTRACT:
A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

REFERENCES:
patent: 3967988 (1976-07-01), Davidsohn
patent: 4635088 (1987-01-01), Eguhi
patent: 5060037 (1991-10-01), Rountree
patent: 5646546 (1997-07-01), Bertolet et al.
Pucknell, D.A., Eshraghian, Kamran; Basic VLSI Design Third Edition; Prentice Hall, Sydney, Austrailia, pp. 176-179, Jan. 1994.

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