Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365190, G11C 1134

Patent

active

055047092

ABSTRACT:
A semiconductor memory device includes a sense amplifier which senses data read out from a memory cell, a transfer gate coupled to an output of the sense amplifier, and a data latch circuit coupled to the transfer gate. The data latch circuit includes two MOS transistors of a same conductivity type connected in series between a pair of I/O data lines. The gates of the two MOS transistors are cross-coupled to the data lines respectively, thereby enabling a rapid data transfer between the memory cell and a data bus.

REFERENCES:
patent: 5220527 (1993-06-01), Ohsawa
patent: 5309389 (1994-05-01), Golke et al.
Publication, "A 100-MHz 4-Mb Cache DRAM with Fast Copy-Back Scheme", Katsumi Dosaka et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 11, November 1992.

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