Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1994-12-08
1996-04-02
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365190, G11C 1134
Patent
active
055047092
ABSTRACT:
A semiconductor memory device includes a sense amplifier which senses data read out from a memory cell, a transfer gate coupled to an output of the sense amplifier, and a data latch circuit coupled to the transfer gate. The data latch circuit includes two MOS transistors of a same conductivity type connected in series between a pair of I/O data lines. The gates of the two MOS transistors are cross-coupled to the data lines respectively, thereby enabling a rapid data transfer between the memory cell and a data bus.
REFERENCES:
patent: 5220527 (1993-06-01), Ohsawa
patent: 5309389 (1994-05-01), Golke et al.
Publication, "A 100-MHz 4-Mb Cache DRAM with Fast Copy-Back Scheme", Katsumi Dosaka et al., IEEE Journal of Solid-State Circuits, vol. 27, No. 11, November 1992.
Miyano Shinji
Sato Katsuhiko
Yabe Tomoaki
Kabushiki Kaisha Toshiba
Popek Joseph A.
LandOfFree
Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2021646