Address comparison in an inteagrated circuit memory having share

Details Address comparison in an inteagrated circuit memory having share Address comparison in an inteagrated circuit memory having share

1995-04-24

1996-11-05

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Multiplexing

36516507, 36518905, 365208, 365190, 3652256, 365177, 36518908, G11C 700

Patent

active

055724671

ABSTRACT:
A synchronous integrated circuit memory (30) has read global data lines shared between data read from a memory array (32) and data read from a data-in register (40) during a read-after-write. A comparator/latch (50) compares a new address to a previous address and generates an address match signal that is used to select match sense amplifiers (52) and deselect regular sense amplifiers (54). Relatively fast address comparison and address match signal generation is accomplished using a comparator/latch (50) for each column address signal, and emitter summing each match signal to provide the address match signal. The use of emitter summing reduces a number of gate delays, thus allowing the address match signal to be generated before the regular sense amplifiers (54) can be selected, and allowing the read global data lines to be shared without increasing the access time of the integrated circuit memory (30).

REFERENCES:
patent: 5502676 (1996-03-01), Pelley, III et al.

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