DRAM having extended refresh time

Details DRAM having extended refresh time DRAM having extended refresh time

1990-10-23

1992-10-20

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

36518901, G11C 1300

Patent

active

051576341

ABSTRACT:
A DRAM is described including a plurality of operable storage cells, each cell including a capacitance for storing a charge indicative of data. The charge tends to dissipate below an acceptable level after a predetermined time interval T1 for a majority of the operable cells and for a minority of the operable cells, it dissipates below the acceptable level after a shorter time interval T2. The time between DRAM refresh cycles is adjusted so as to be greater than time interval T2. The DRAM comprises: a plurality of redundant storage cells; a decoder for receiving the address of an operable memory cell and providing a first output if the address indicates one of the operable cells of the minority of cells and a second output if the address indicates one of the operable cells of the majority. A switching circuit is responsive to the first output to enable access of a redundant stoarge cell and to prevent access of the minority storage cell. In a preferred embodiment, the redundant storage cells are configured as static storage circuits.

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Guttmann et al., "Refresh Test of Dynamic Ram", IBM Technical Disclosure Bulletin, vol. 28, No. 5, Oct. 1985, pp. 2172-2173.

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