CMOS device structure with reduced risk of salicide bridging and

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257344, 257345, 257371, 257384, 257413, 257900, H01L 2978, H01L 27092

Patent

active

057570450

ABSTRACT:
A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used to reduce punchthrough leakage. An ultra shallow junction extension region has been created in a peripheral channel region, reducing the resistance of this region, thus enhancing the performance of the CMOS device. In addition, ultra lightly doped source and drain regions are used to relax reliability concerns, regarding hot electron injection.

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