Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-12-13
2000-10-24
Smith, Matthew
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438239, 438254, 438255, 438256, H01L 18242
Patent
active
061366447
ABSTRACT:
A method for forming a dynamic random access memory cell with an increased capacitance capacitor having a multi-pillared storage node is achieved. A first layer of polysilicon fills an opening through a first dielectric layer to a node contact region. A photoresist mask is formed over the portion of a second dielectric layer over the polysilicon layer over the node contact region. The photoresist mask is silylated. The top silylated photoresist portion is removed. The second dielectric layer and the first polysilicon layer are etched away where they are not covered by the photoresist mask and the silylated photoresist sidewalls thereby forming a T-shaped first polysilicon layer. The photoresist mask is removed whereby the silylated photoresist sidewalls remain. The second dielectric layer is etched away where it is not covered by the silylated photoresist sidewalls thereby forming dielectric bars underlying the sidewalls and exposing the first polysilicon layer between the dielectric bars. The silylated photoresist sidewalls are removed. A second polysilicon layer is deposited and anisotropically etched back to leave polysilicon pillars on either side of the dielectric bars wherein the polysilicon pillars contact the T-shaped first polysilicon layer. The dielectric bars are removed whereby the T-shaped first polysilicon layer and the polysilicon pillars form a storage node of the capacitor.
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Hsu Huei-Wen
Lin Su-fen
Tseng Horng-Huei
Ackerman Stephen B.
Pike Rosemary L. S.
Saile George O.
Smith Matthew
Vanguard International Semiconductor Corporation
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