Method of fabricating an EPROM cell with a high coupling ratio

Details Method of fabricating an EPROM cell with a high coupling ratio Method of fabricating an EPROM cell with a high coupling ratio

1997-05-20

1998-05-26

Niebling, John

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438593, 438594, 438596, H01L 218247

Patent

active

057563845

ABSTRACT:
A method of forming an EPROM with a high capacitive coupling ratio is disclosed. The method includes forming a tunnel oxide layer on the substrate. A first polysilicon layer is then formed over the tunnel oxide layer. A dielectric layer is deposited on the first polysilicon layer. Then, the layers are patterned and etch to form a stacked structure. A lateral etching is performed to etch portions of the first polysilicon layer. Next, a second polysilicon layer is formed along the surface of the first polysilicon layer, the tunnel oxide and the dielectric layer. An anisotropic etching process is carried out to anisotropically etch the second polysilicon layer. The dielectric layer is then removed by wet etching. Subsequently, a inter-poly dielectric layer is formed along the surface of first polysilicon layer and the second polysilicon layer. A third polysilicon layer is then formed along the surface of the inter-poly dielectric layer. Finally, an etching process is used using a photoresist as an etching mask to etch the inter-poly dielectric layer and the third polysilicon layer.

REFERENCES:
patent: 5053849 (1991-10-01), Izawa et al.
patent: 5498560 (1996-03-01), Sharma et al.
patent: 5543339 (1996-08-01), Roth et al.
patent: 5559049 (1996-09-01), Cho
patent: 5567637 (1996-10-01), Hirota

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