Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-10-09
1998-05-26
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438303, 438305, 438306, 257336, 257344, 257408, 257900, H01L 218238
Patent
active
057563810
ABSTRACT:
A semiconductor device having a lightly doped drain ("LDD") at a first dopant concentration and a source side extension ("SSE") at a second, higher, dopant concentration is provided. This allows for increased current saturation .vertline..sub.DSAT due to a lower resistance at or near the source and thus increases semiconductor switching speed without hot carrier creation due to lighter doped, more graded body-drain junction. A method for manufacturing the semiconductor device, in particular a metal oxide semiconductor ("MOS") transistor, is also provided. A first photoresist mask is positioned over a portion of a polysilicon gate and a subsequently formed drain region of a transistor substrate. The transistor may be an N-channel or P-channel transistor. The SSE is formed using a higher dopant concentration than used in the LDD. A second photoresist mask is then used to cover the SSE region and portion of the polysilicon gate while a relatively lower implant dopant dose is used to form the LDD. Oxide spacers and heavy implant concentrations are then used to form a source and a drain.
REFERENCES:
patent: 5013675 (1991-05-01), Shen et al.
patent: 5200351 (1993-04-01), Hadjizadeh-Amini
patent: 5338960 (1994-08-01), Beasom
Advanced Micro Devices , Inc.
Niebling John
Pham Long
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