Method of fabricating an integrated circuit including a tri-laye

Details Method of fabricating an integrated circuit including a tri-laye Method of fabricating an integrated circuit including a tri-laye

1995-11-16

2000-10-03

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438699, H01L 21316

Patent

active

061272612

ABSTRACT:
A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed.

REFERENCES:
patent: 4394401 (1983-07-01), Shioya et al.
patent: 4791071 (1988-12-01), Ang
patent: 4877641 (1989-10-01), Dory
patent: 5041311 (1991-08-01), Tsukune et al.
patent: 5068124 (1991-11-01), Batey et al.
patent: 5275963 (1994-01-01), Cederbaum et al.
patent: 5284789 (1994-02-01), Mori et al.
patent: 5405710 (1995-04-01), Dodabalapur et al.
patent: 5464794 (1995-11-01), Lur et al.
patent: 5482749 (1996-01-01), Telford et al.
patent: 5508534 (1996-04-01), Nakamura et al.
patent: 5510652 (1996-04-01), Burke et al.
patent: 5560802 (1996-10-01), Chisholm
patent: 5578860 (1996-11-01), Costa et al.
patent: 5583360 (1996-12-01), Roth et al.
patent: 5627403 (1997-05-01), Bacchetta et al.
patent: 5635417 (1997-06-01), Natsume
patent: 5736423 (1998-04-01), Ngo
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2, pp. 198-199, 1990.
Lee, Hong H., Fundamentals of microelectronics processing, pp. 394-395, 420-424, 449, 1990.
S. Wolf et al. Silicon Processing for the VLSI Era. vol. 1, p. 164, 514, 1986.
S. Wolf et al. Silicon Processing for the VLSI Era, vol. 2, p. 226, 238-239, 1990.
M.K. Jain et al. "Chemical Mechanical Planarization of Multilayer Dielectric Stacks", SPIE: Microelectronics Technology and Process Integration, Oct. 20-21, 1994, Austin, Texas, pp. 2-1, XP002019336.
"SI Precoat of PECVD Chamber Walls Prior to the Formation of a Thin SI Layer on Gas or III-V Compounds", Research Disclosure, No. 325, May 1, 1991, p. 367 XP000229723.

Affiliated with

Also associated with

Rating

Method of fabricating an integrated circuit including a tri-laye does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating an integrated circuit including a tri-laye, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating an integrated circuit including a tri-laye will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-194906