Method of reducing overlap between gate electrode and LDD region

Details Method of reducing overlap between gate electrode and LDD region Method of reducing overlap between gate electrode and LDD region

1996-04-26

1999-02-09

Brown, Peter Toby

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438287, 438306, 438307, H01L 21336

Patent

active

058693785

ABSTRACT:
A method of manufacturing an integrated circuit so as to reduce overlap between an LDD region and a gate electrode is disclosed. The method includes forming a gate electrode on a gate insulator on a semiconductor substrate, implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask, removing a lateral portion of the gate electrode after implanting the LDD region, and then laterally diffusing the LDD region into the substrate such that a lateral edge of the LDD region is substantially aligned with a lateral edge of the gate electrode. Preferably, the lateral portion of the gate electrode is removed using an isotropic etch. The method further includes forming a spacer adjacent to an edge of the gate electrode after removing the lateral portion, and then implanting a heavily-doped region using the spacer and gate electrode as an implant mask.

REFERENCES:
patent: 4402761 (1983-09-01), Feist
patent: 4486943 (1984-12-01), Ryden et al.
patent: 4722909 (1988-02-01), Parrillo et al.
patent: 5340774 (1994-08-01), Yen
patent: 5462884 (1995-10-01), Taniguchi

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