Method of fabricating semiconductor devices with self-aligned si

Details Method of fabricating semiconductor devices with self-aligned si Method of fabricating semiconductor devices with self-aligned si

1998-05-06

2000-02-15

Wilczewski, Mary

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438595, 438649, 438655, 438695, 438660, 438664, 438682, 148DIG147, 257382, 257383, 257757, 257768, 257770, H01L 21336, H01L 2128

Patent

active

060252413

ABSTRACT:
A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer. Through this method, the resultant semiconductor device is reliable in operation since the drawback of the occurrence of leakage current or short-circuit that could be otherwise resulted between the self-aligned silicide and the substrate owing to the short-channel effect can be eliminated. Moreover, the resultant semiconductor device has increased anti-static capability that can protect the semiconductor device against electro-static damage.

REFERENCES:
patent: 5102816 (1992-04-01), Manukonda et al.
patent: 5416048 (1995-05-01), Blalock et al.
patent: 5759901 (1998-06-01), Loh et al.
patent: 5824588 (1998-10-01), Liu
patent: 5858848 (1999-01-01), Gardner et al.
patent: 5879999 (1999-03-01), Park et al.

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