Method of forming a capacitor and a capacitor formed using the m

Details Method of forming a capacitor and a capacitor formed using the m Method of forming a capacitor and a capacitor formed using the m

1998-01-15

2000-02-15

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438600, 438633, H01L 218242

Patent

active

06025226&

ABSTRACT:
An integrated circuit including a capacitor and a method of manufacturing the capacitor simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings corresponding to vias and capacitors extend through a second interlevel dielectric to the first interconnect layer. A conductor is deposited in the via openings. An insulator is deposited in the openings and on the conductor in the via openings. A trench is then etched into the upper portion of the via openings while simultaneously removing the insulator from the conductor in the via openings. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

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