Method of forming a polysilicon diode and devices incorporating

Details Method of forming a polysilicon diode and devices incorporating Method of forming a polysilicon diode and devices incorporating

1996-06-18

2000-02-15

Mulpuri, Savitri

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438702, 438238, H01L 2170

Patent

active

060252200

ABSTRACT:
A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.

REFERENCES:
patent: 3423646 (1969-01-01), Cubert et al.
patent: 3796926 (1974-03-01), Cole et al.
patent: 4099260 (1978-07-01), Lynes et al.
patent: 4115872 (1978-09-01), Bluhm
patent: 4174521 (1979-11-01), Neale
patent: 4194283 (1980-03-01), Hoffmann
patent: 4203123 (1980-05-01), Shanks
patent: 4227297 (1980-10-01), Angerstein
patent: 4272562 (1981-06-01), Wood
patent: 4458260 (1984-07-01), McIntyre et al.
patent: 4502208 (1985-03-01), McPherson
patent: 4569698 (1986-02-01), Feist
patent: 4715109 (1987-12-01), Bridges
patent: 4757359 (1988-07-01), Chiao et al.
patent: 4804490 (1989-02-01), Pryor et al.
patent: 4809044 (1989-02-01), Pryor et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4876668 (1989-10-01), Thakoor et al.
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 4892840 (1990-01-01), Esquivel et al.
patent: 5144404 (1992-09-01), Iranmanesh et al.
patent: 5166096 (1992-11-01), Cote et al.
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 5177567 (1993-01-01), Klersy et al.
patent: 5236863 (1993-08-01), Iranmanesh
patent: 5250461 (1993-10-01), Sparis
patent: 5296716 (1994-03-01), Ovshinsky et al.
patent: 5308783 (1994-05-01), Krautschneider et al.
patent: 5316978 (1994-05-01), Boyd et al.
patent: 5335219 (1994-08-01), Ovshinsky et al.
patent: 5341328 (1994-08-01), Ovshinsky et al.
patent: 5359205 (1994-10-01), Ovshinsky
patent: 5510629 (1996-04-01), Karpovich et al.
patent: 5583348 (1996-12-01), Sundaram
patent: 5700712 (1997-12-01), Schwalke
patent: 5751012 (1998-05-01), Wolstenholme et al.
patent: 5814150 (1998-11-01), Gonzalez et al.
patent: 5831276 (1998-11-01), Gonzalez et al.
Kim and Kim, "Effects of High-Current Pulses on Polycrystalline Silicone Diode with n-type Region Heavily Doped with Both Boron and Phosphorus," J. Appl. Phys., 53(7):5359-5360, 1982.
Neale and Aseltine, "The Application of Amorphous Materials to Computer Memories," IEEE, 20(2):195-205, 1973.
Pein and Plummer, "Performance of 3-D Sidewall Flash EPROM Cell," IEEE, 11-14, 1993.
Post and Ashburn, "Investigation of Boron Diffusion in Polysilicon and its Application to the Design of p-n-p Polysilicon Emitter Bipolar Transistors with Shallow Emitter Junctions," IEEE, 38(11):2442-2451, 1991.
Post et al., "Polysilicon Emitters for Bipolar Transistors: A Review and Re-Evaluation of Theory and Experiment," IEEE, 39(7):1717-1731, 1992.
Post and Ashburn, "The Use of an Interface Anneal to Control the Base Current and Emitter Resistance of p-n-p Polysilicon Emitter Bipolar Transistors," IEEE, 13(8):408-410, 1992.
Rose et al., "Amorphous Silicon Analogue Memory Devices," J. Non-Crystalline Solids, 115:168-170, 1989.
Schaber et al., "Laser Annealing Study of the Grain Size Effect in Polycrystalline Silicon Schottky Diodes," J. Appl. Phys., 53(12):8827-8834, 1982.
Yamamoto et al., "The I-V Characteristics of Polycrystalline Silicon Diodes and the Energy Distribution of Traps in Grain Boundaries," Electronics and Communications in Japan, Part 2, 75(7):51-58, 1992.
Yeh et al., "Investigation of Thermal Coefficient for Polycrystalline Silicon Thermal Sensor Diode," Jpn. J. Appl. Phys., 31(Part 1, No. 2A):151-155,1992.
Yeh et al., "Investigation of Thermal Coefficient for Polycrystalline Silicon Thermal Sensor Diode," Jpn. J. Appl. Phys., 31(Part 1, No. 2A):151-155, 1992.
Oakley et al., "Pillars--The Way to Two Micron Pitch Multilevel Metallisation," IEEE, 23-29, 1984.

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