Method for forming a multilayer wiring of a semiconductor device

Details Method for forming a multilayer wiring of a semiconductor device Method for forming a multilayer wiring of a semiconductor device

1991-07-29

1993-10-12

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156657, 156656, 156667, 20419232, 437228, 437235, B44C 122, C23F 700

Patent

active

052521770

ABSTRACT:
A method for forming a multilayer wiring, in a method for manufacturing a semiconductor device, is disclosed. The method comprises: forming a contact hole 33 on the surface of a conductive layer 29 by a photolithography, removing a photoresist by using plasma ashing at a predetermined temperature, pressure and amount of oxygen per unit cubic, and simultaneously forming a protective layer 35 consisting of a oxide layer on the surface of the exposed conductive layer. Thus, damage of the surface of wiring caused by the chemical reaction of an organic solvent and water in the subsequent process thereof, is prevented, to provide high density and high speed semiconductor integrated circuit whose electrode characteristics between two wiring layers is improved.

REFERENCES:
patent: 4857141 (1989-08-01), Abe et al.

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