Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1998-04-21
1999-05-04
Phan, Trong
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518908, 365207, 365233, G11C 1604, G11C 702, G11C 800
Patent
active
059010916
ABSTRACT:
There is disclosed a bidirectional data input/output circuit of a synchronous memory device and the method for controlling the same according to the present invention. The synchronous memory device according to the present invention is aimed at solving a data confusion problem generated when a write operation subsequent to a data read operation is performed in a data input/output line. Though the data line is a bidirectional bus data line by which an input/output is also performed, it can be applied to a circuit construction in which high and low potential data are inputted/outputted through an independent dedicated line. In addition, there is provided an internal buffer for inputting a write data into the memory device. The circuit according to the present invention further includes a memory for storing a data signal generated upon a read operation, when a read operation subsequent in time to a write operation is performed; and a device for selecting as a write data the opposite signal of the data signal generated upon a read operation when the two data lines both become active.
REFERENCES:
patent: 5278789 (1994-01-01), Inoue et al.
patent: 5608688 (1997-03-01), Park
patent: 5657292 (1997-08-01), McClure
patent: 5742544 (1998-04-01), Foss
patent: 5754488 (1998-05-01), Suh
Hyundai Electronics Industries Co,. Ltd.
Nath Gary M.
Phan Trong
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