Method to form a capacitor for high density DRAM cell

Details Method to form a capacitor for high density DRAM cell Method to form a capacitor for high density DRAM cell

1998-02-13

1999-05-04

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 218242

Patent

active

058997156

ABSTRACT:
A new method for the manufacturing of a capacitor for a DRAM is disclosed herein. The method for manufacturing a capacitor on a semiconductor wafer including the following steps. Firstly, sequentially forming a first dielectric layer, a first conductive layer, a second dielectric layer and a third dielectric layer formed on the semiconductor wafer. Secondary, the third dielectric layer and a portion of the second dielectric layer are etched. The portion of the second dielectric layer is isotropically etched to form a hemispherical cavity. Next, the second dielectric layer, the first conductive layer and the first dielectric layer is etched sequentially to form a hole in contact with a portion of the semiconductor wafer by using the third dielectric layer as a mask. Subsequently, the third dielectric layer is removed when etching the first dielectric layer. Afterword, a second conductive layer is formed on the second dielectric layer and in the hole. Next, a pattern for an underlying electrode is formed by anisotropically etching a portion of the second conductive layer, the second dielectric layer and the first conductive layer. Successively, the first dielectric layer is isotropically etched, and a fourth dielectric layer is formed on the underlying electrode. Finally, a third conductive layer is formed on the fourth dielectric layer to form an upperlying electrode of the capacitor.

REFERENCES:
patent: 5180689 (1993-01-01), Liu et al.
patent: 5384276 (1995-01-01), Ogawa et al.

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