Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-12-31
1998-12-08
Nelms, David
Static information storage and retrieval
Read/write circuit
Testing
36518902, 36518907, G11C 700
Patent
active
058480161
ABSTRACT:
An integrated circuit having a wide internal data path, such as a Merged Memory and Logic (MML) integrated circuit, is tested by serially comparing data on one of the data paths to data on selected others of the data paths. A first indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are all a first logic value. A second indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are all a second logic value. A third indication is provided if the serially compared data on the one of the data paths and on the selected others of the data paths are of differing logic values. By serially comparing data on one of the data paths to data on selected others of the data paths, a reduced number of comparators may be provided. Efficient circuits and methods for testing integrated circuits, such as memory integrated circuits or logic integrated circuits, may thereby be provided.
REFERENCES:
patent: 5164918 (1992-11-01), Ogino et al.
patent: 5400281 (1995-03-01), Morigami
patent: 5430677 (1995-07-01), Fandrich et al.
patent: 5483493 (1996-01-01), Shin
Mai Son
Nelms David
Samsung Electronics Co,. Ltd.
LandOfFree
Merged Memory and Logic (MML) integrated circuits and methods in does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Merged Memory and Logic (MML) integrated circuits and methods in, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Merged Memory and Logic (MML) integrated circuits and methods in will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-185379