Dynamic memory with on-chip refresh invisible to CPU

Details Dynamic memory with on-chip refresh invisible to CPU Dynamic memory with on-chip refresh invisible to CPU

1979-10-05

1982-06-01

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

G11C 700, G11C 1140

Patent

active

043331670

ABSTRACT:
A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh circuitry which automatically produces a refresh operation invisible to the CPU. The refresh circuitry includes an address counter and a multiplexer to insert the refresh address when an internal clock indicates a refresh cycle. The refresh address counter is incremented after each refresh cycle. If a refresh command is being executed when an address presented, the refresh operation is completed then the device is accessed in the usual manner. By specifying the access time of the device as the sum of the usual access type plus the time needed for refresh, the internal refresh is invisible to the CPU.

REFERENCES:
patent: 4040122 (1977-08-01), Bodin
patent: 4112514 (1978-09-01), Spoelder
patent: 4290120 (1981-09-01), Stein

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