Method for making shallow trench isolation structure having roun

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

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438701, 438740, H01L 2176

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057535612

ABSTRACT:
Disclosed is a method for making a shallow trench structure in a semiconductor substrate. The method includes: (a) forming a mask over a semiconductor substrate, the mask being provided with an aperture extending therethrough which exposes a region of the semiconductor substrate, the aperture having substantially vertical sidewalls; (b) depositing a blanket of silicon over the mask and within the aperture; (c) anisotropically etching the deposited silicon to form temporary spacers having curved profiles at the sidewalls of the aperture, the temporary spacers transferring the curved profiles to a mouth of a shallow trench being etched at the region of the semiconductor substrate as the temporary spacers are etched away; (d) whereby a shallow trench structure is formed where the mouth has a curved profile.

REFERENCES:
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patent: 5403770 (1995-04-01), Jang
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patent: 5567270 (1996-10-01), Liu
Andres Bryant, W. Haensch, S. Geissler, Jack Mandelman, D. Poindexter, and M. Steger, "The Current-Carrying Corner Inherent to Trench Isolation,"IBM Technology, Vermont and New York, IEEE Log #9211204, May 16, 1993.
Adler, DeBrosse, Geissler, Holmes, Jaffe, Johnson, Koburger, Lasky, Lloyd, Miles Nakos, Noble, Jr., Voldman, Armacost, and Ferguson, "The Evolution of IBM CMOS DRAM Technology,"vol. 39, No. 1/2, Journal of Research and Development, Oct. 14, 1994.

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