Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

Patent

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Details

365210, 357 45, G11C 1140

Patent

active

043143601

ABSTRACT:
A semiconductor memory device comprising a memory cell array consisting of a plurality of cell transistors, and additional transistors connected between bit lines and a reference potential point for suppressing the lowering of the potential of a bit line when said semiconductor memory device is changed from a non-operative state to an operative state.

REFERENCES:
patent: 4112508 (1978-09-01), Itoh

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