Method of manufacturing dual-packed capacitor for DRAM cells

Details Method of manufacturing dual-packed capacitor for DRAM cells Method of manufacturing dual-packed capacitor for DRAM cells

1996-10-25

1999-09-07

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438241, H01L 218242

Patent

active

059500840

ABSTRACT:
Manufacturing dual-packed capacitor DRAM cells with the storage capacitors of two memory cells stacked one over the other and formed on a common trench so as to increase capacitance while decreasing area occupation by the capacitors includes forming a trench on a semiconductor substrate, forming an insulating layer above the semiconductor substrate surface covering the bottom and side walls of the trench, forming a first opening in the insulating layer exposing part of the semiconductor substrate adjacent to one side of the trench, forming a first storage electrode inside the trench above the surface of the insulating layer, which extends into the first opening and contacts the semiconductor substrate, forming a first dielectric layer above the surface of the first storage electrode, forming a common opposed electrode above the first dielectric layer which includes a vertical main section inserted into the trench, a horizontal main plate, and at least one extended section protruding vertically upward, forming a second dielectric layer covering an exposed surface of the common exposed electrode, forming a second opening in the insulating layer exposing part of the semiconductor substrate surface adjacent to another side of the trench, forming a second storage electrode above the second dielectric layer, and extending into the second opening contacting the semiconductor substrate, removing the exposed part of the insulating layer; forming a pair of pass transistors symmetrically on opposite sides of the trench, wherein the respective drain regions of the pass transistors are disposed nearest the trench and each is electronically coupled with a respective storage electrode.

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